ASIC Design Classroom Training and Certification Classes

• Full-custom ASICs
• Semi-Custom ASICs including Standard Cell-based and Gate-array based (Channeled, Channelless and Structured Gate)
• Programmable ASICs including PLDs and FPGAs

Design flow is a sequence of steps to design an ASIC.

• Design flow
• Design entry
• Logic synthesis
• System partitioning
• Pre-layout simulation
• Floor planning
• Placement
• Routing
• Extraction
• Post-layout simulation

Power stripes are routed in the top metal layers because the resistivity of top metal layers is less and, therefore, less IR drop is seen in power distribution network. If the power stripes are routed in the lower metal layers, it can create routing congestion.

Alternate routing approach is used because it allows routability of the design and better usage of routing resources.

• Logic optimization: buffer sizing, cell sizing, level adjustment, dummy buffering etc.
• Less number of logics between Flip Flops speedup the design.
• Optimize drive strength of the cell , so it is capable of driving more load and hence reducing the cell delay.
• Better selection of design ware component (select timing optimized design ware components).
• Use LVT (Low threshold voltage) and SVT (standard threshold voltage) cells if allowed.

set_clock_uncertainty –from clock1 -to clock2

Low Power Design Techniques